The present invention relates, in general, to the design and testing of integrated circuits and, more specifically, to a of circuit scan testing method which provides real time identification of failing test patterns or small blocks of test patterns.
Scan testing of integrated circuits (ICs) generally involves loading test patterns or vectors into scannable memory elements of the circuit, capturing the response of the circuit to the test patterns, unloading the test response from the memory elements. Conventional scan techniques have a number of limitations in terms of the large amount of test data that need to be stored and frequencies at which the test patterns can be applied. Embedded test methods address these limitations by providing on-chip circuitry to generate patterns and analyze their output response. The output can be analyzed by compressing the test response into a signature register and then comparing the signature obtained with an expected signature. A set or block of test patterns fails when the actual signature obtained and the expected signature are different. Typically, a plurality of test patterns are executed and only the final signature is compared with a final expected signature. A major advantage of using embedded test methods is that simply comparing the final signature with an expected final signature is sufficient to determined whether any patterns resulted in failures. This provides for a very low volume of test data, but it not very efficient when a list of failing patterns is required. For example, such list is needed to determine which patterns tend to fail more often than others. Diagnosis can be performed to identify the root cause of the failures which could be due to an uncontrolled process or a design error.
It would be desirable to be able to identify failing test patterns, or small blocks of test patterns having a failing pattern, in real time. There are several problems that must be addressed in order to find all failing patterns in one pass through all patterns. First, signature values must be observed and/or compared after execution of each pattern (or trial) or small block of patterns. Second, a failure in one pattern must not influence the resulting signatures in the following patterns. Third, the transfer of information between the test controller(s), possibly running at high speed, and the tester must be synchronized without increasing test time, requiring to contact a large number of circuit pins, increasing pin accuracy requirements on the tester, lowering test quality, significantly increasing the routing and gate count requirements of a test controller, losing any flexibility in terms of how several test controllers can run concurrently, or having to generate new test data.
Forlenza et al U.S. Pat. No. 5,930,270 granted on Jul. 27, 1999 for xe2x80x9cLogic Built In Self-Test Diagnostic Methodxe2x80x9d, partially addresses the problems listed above. However, it falls short of addressing all the requirements. For example, the MISR is reset between each interval. An interval is a block of patterns or vectors. This means that the signatures generated for a given pattern are different depending on the size of the intervals. This requires generating a significant amount of new test data. Another major limitation is that the synchronization between the test controller and the external tester is addressed by using the same clock. This means that the test controller(s) cannot be operated at their respective speed. This is clearly not acceptable from the points of view of test time and/or test quality. The method also does not scale when several test controllers are running concurrently because the expected signatures (called xe2x80x9cGood Machine Signaturesxe2x80x9d or GMS by Forlenza et al) are transferred using a parallel data interface because too many pins would need to be contacted.
There is clearly a need for a more efficient method of providing real time identification of failing test patterns.
The present invention provides a scan-based embedded test method and corresponding circuit which allows identifying failing test patterns or small blocks of patterns without increasing test time or calculating new expected signatures as compared to a GO/NO-GO test. One or more controllers can execute test patterns using high speed clocks, but the transfer of information between the test controller(s) can be performed using a low speed clock. Only a small number of circuit pins need to be contacted and low accuracy pin electronics can be used. The additional circuitry required by the method is small.
One aspect of the present invention is generally defined as a method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern, comprising performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.
Another aspect of the present invention is generally defined as a test controller for use in self-testing of an integrated circuit under control of a first clock and providing real time identification of blocks of test patterns having at least one failing test pattern, the controller having a test response signature register for storing a compressed test response of the circuit to a block of test patterns, the improvement comprising an expected signature register having a serial input and a serial output, and a control circuit for controlling loading of an expected signature into the expected signature register under control of a test clock and for replacing the contents of the test response signature register with the contents of the expected signature register.